Configuration File Generation For Fracturable Data Path In A Coarse-Grained Reconfigurable Processor

A method for producing a configuration file to configure a fracturable data path of a configurable unit in an array of configurable units of a coarse-grained reconfigurable processor to generate a plurality of independent address sequences including a first address sequence generated using a first address calculation and a second address sequence generated using a second address calculation, the fracturable data path comprising a plurality of pipelined computation stages, the method comprising:

• analyzing the first address calculation and the second address calculation to determine to use N pipeline stages for the first address calculation and M pipeline stages for the second address calculation, wherein N and M are positive integers;
• generating first configuration data for a first set of stages to produce the first address sequence and second configuration data for a second set of stages to generate the second address sequence, the first set of stages consisting of N computational stages of the plurality of pipelined computation stages and the second set of stages consisting of M computational stages of the plurality of pipelined computation stages;
• and
• including the first configuration data and the second configuration data in the configuration file.

A data processing system comprising:

• a compiler designed to produce a configuration file to configure a fracturable data path of a configurable unit in an array of configurable units of a coarse-grained reconfigurable processor to generate a plurality of independent address sequences including a first address sequence generated using a first address calculation and a second address sequence generated using a second address calculation, the fracturable data path comprising a plurality of pipelined computation stages, the compiler further configured to:
• analyze the first address calculation and the second address calculation to determine to use N pipeline stages for the first address calculation and M pipeline stages for the second address calculation, wherein N and M are positive integers;
• generate first configuration data for a first set of stages to produce the first address sequence and second configuration data for a second set of stages to generate the second address sequence, the first set of stages consisting of N computational stages of the plurality of pipelined computation stages and the second set of stages consisting of M computational stages of the plurality of pipelined computation stages;
• and
• include the first configuration data and the second configuration data in the configuration file.