Memory core and semiconductor apparatus with transposed matrix calculation function including the same
AssigneeSK hynix Inc.
InventorsGi Moon HONG, Dae Han KWON
Life of this patent
Estimating the term…
Abstract
A memory core includes a first signal line; a second signal line; a first transistor coupled between the second signal line and a data storage element; a second transistor coupled between the first signal line and the data storage element; and a switching circuit configured to, in response to a mode selection signal, switch an operation of the memory core between a first mode and a second mode, the first mode controlling the first transistor according to a level of the first signal line and turning off the second transistor and a second mode controlling the second transistor according to a level of the second signal line and turning off the first transistor.
Claims16
A memory core comprising:
- a first signal line;
- a second signal line;
- a first transistor coupled between the second signal line and a data storage element;
- a second transistor coupled between the first signal line and the data storage element;
- and
- a switching circuit configured to, in response to a mode selection signal, switch an operation of the memory core between a first mode and a second mode, the first mode controlling the first transistor according to a level of the first signal line and turning off the second transistor and the second mode controlling the second transistor according to a level of the second signal line and turning off the first transistor.
A semiconductor apparatus comprising:
- a memory core including a plurality of unit memory regions having a plurality of unit cells coupled between a plurality of first signal lines and a plurality of second signal lines, wherein each of the plurality of unit cells is configured to perform data input/output (I/O) according to a level of a corresponding first signal line through a corresponding second signal line when an operation mode of the memory core is set to a first mode and configured to perform data I/O according to a level of the corresponding second signal line through the corresponding first signal line when the operation mode of the memory core is set to a second mode;
- a data I/O circuit coupled between the memory core and an I/O pad circuit;
- and
- a control circuit configured to, in response to a transposed matrix calculation command, perform a transposed matrix calculation by controlling mode switching between the first mode and the second mode and a data exchange between the plurality of unit memory regions and the data I/O circuit.
A memory core comprising:
- a word line and a bit line arranged in a matrix form;
- a a first transistor coupled between the bit line and a data storage element;
- a second transistor coupled between the word line and the data storage element;
- and
- a switching circuit configured to:
- control the first transistor according to a level of the word line and turn off the second transistor when a mode selection signal has a level defining an operation mode of the memory core as a first mode and
- control the second transistor according to a level of the bit line and turn off the first transistor when the mode selection signal has a level defining the operation mode of the memory core as a second mode.
Dependencies are inferred from the claim text.