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US 2024/0192874 A1Published application
Apparatuses and methods for shared row and column address buses
AssigneeMicron Technology, Inc.
InventorsHiroshi Akamatsu, Reuben Pradhan
Life of this patent
Estimating the term…
Abstract
Apparatuses and methods for shared row and column address buses. Row and column addresses are distributed along separate respective global buses in a central logic region of a memory. The row and column addresses are coupled through a shared address bus from the central logic region to a bank logic region. For example the row address may be provided along the shared address bus at a first time and the column address may be provided along the shared address bus at a second time.
Claims20
An apparatus comprising:
- a first latch configured to receive a row address from a row address bus;
- a second latch configured to receive a column address from a column address bus, wherein the first latch and the second latch are located in a central logic region;
- a multiplexer configured to provide the row address from the first latch or the column address from the second latch along a shared bus from the central logic region to a bank logic region.
An apparatus comprising:
- a bank logic region associated with a memory bank;
- a central logic region including a row address bus and a column address bus;
- a shared address bus coupling the central logic region to the bank logic region;
- and
- a multiplexer configured to couple the row address bus or the column address bus to the shared address bus.
2 more elements
A method comprising:
- providing a row address along a row address bus in a central logic region;
- providing the row address along a shared bus from the central logic region to a bank logic region responsive to a row activation signal;
- providing a column address along a column address bus in the central logic region;
- and
- providing a column address along the shared bus responsive to a read or write command.
2 more elements
Dependencies are inferred from the claim text.