Feed forward training of memory interfaces
AssigneeAdvanced Micro Devices, Inc.
InventorsAaron D. Willey, Karthik Gopalakrishnan, Pradeep Jayaraman
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Abstract
A data processor, system, method, integrated circuit are provided which update timing values for accessing a memory to compensate for voltage and temperature (VT) drift during operation. The method includes performing a link retraining sequence for a plurality of DQ lanes of the memory bus and determining a first phase offset based on the link retraining. The method includes calculating a second offset based on the first offset, applying the second offset to a plurality of command CA lanes of the memory bus.
Claims20
A data processing system comprising a data processor coupled to a memory, the data processor comprising:
- a physical layer circuit (PHY) for coupling to a memory bus;
- a calibration circuit for performing a link retraining sequence for a plurality of data (DQ) lanes of the memory bus and determining a first phase offset based on the link retraining;
- and
- a compensation circuit for calculating a second offset based on the first offset,
- wherein the calibration circuit is further operable to apply the second offset to a plurality of command/address (CA) lanes of the memory bus.
A method for a data processor to update timing values for accessing a memory to compensate for voltage and temperature (VT) drift during operation, comprising:
- performing a link retraining sequence for a plurality of data (DQ) lanes of the memory bus and determining a first phase offset based on the link retraining;
- calculating a second offset based on the first offset;
- and
- applying the second offset to a plurality of command/address (CA) lanes of the memory bus.
An integrated circuit comprising:
- a physical layer circuit (PHY) for coupling to a memory bus;
- a calibration circuit for performing a link retraining sequence for a plurality of data (DQ) lanes of the memory bus and determining a first phase offset based on the link retraining;
- and
- a compensation circuit for calculating a second offset based on the first offset,
- wherein the calibration circuit is further operable to apply the second offset to a plurality of command/address (CA) lanes of the memory bus.
Dependencies are inferred from the claim text.