Method to manage periodic dram refresh and maintenance scheduling for predictable dram data access
AssigneeGroq, Inc.
InventorsAlbert Cheng, Michael Bye, Rahul Shah
Life of this patent
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Abstract
When reading and writing DRAM (dynamic random-access memory), the latency and bandwidth is often unpredictable with large variations. One reason is because all the DRAM memory banks require periodic refreshes and maintenance cycles that interrupt these accesses. DRAM refresh and maintenance cycles are synchronized with the read/write accesses in a mutually exclusive manner, hence, preventing the accesses from being interfered with by a refresh or maintenance cycle resulting in predictable latency and bandwidth performance during read/write operations.
Claims22
A computer system for executing a program on a processor comprising a compiler for generating an explicit plan for how the processor will execute the program by specifying a deterministic schedule wherein the explicit plan for execution includes information for explicit prediction of when data will be read from an external memory while executing the program.
A method for executing a program on a processor comprising a compiler for generating an explicit plan for how the processor will execute the program by specifying a deterministic schedule wherein the explicit plan for execution includes information for explicit prediction of when data will be read from an external memory while executing the program.
A computer system for executing a program on a processor comprising:
- a compiler for generating an explicit plan for how the processor will execute the program by specifying a deterministic schedule wherein the explicit plan for execution includes information for explicit prediction of when data will be read from an external memory while executing the program;
- and
- a DRAM controller provides a request window based on a deterministic schedule wherein the explicit plan for execution includes information for explicit prediction of when data will be read from an external memory or written to the external memory while executing the program wherein the deterministic schedule processor directs the DRAM controller to selectively:
- 1) issue refresh/maintenance cycles according to the deterministic schedule;
- or
- 2) the DRAM controller adheres to a fixed, known refresh/maintenance schedule that the processor is aware of;
- or
- 3) processor uses a fixed, known access schedule that the DRAM controller is aware of;
- or
- 4) the DRAM controller and the computer system employ a scheduling approach that is a combination of more than one approach wherein the processor and the DRAM controller work in a synchronous manner to avoid collisions between DRAM access requests from the processor and the refresh/maintenance cycles to the DRAM issued by the DRAM controller.
A method to manage periodic refresh and maintenance scheduling for a DRAM array to obtain a predictable DRAM data access behavior so that the DRAM array operates in a deterministic manner in conjunction with a deterministic processor.
Dependencies are inferred from the claim text.