Architecture for managing asynchronous resets in a system-on-a-chip

A method, comprising:

• based at least in part on a clock signal and an indication to reset, enabling a first reset signal of a System-On-a-Chip (SoC), wherein the first reset signal is provided to a first portion of a component of the SoC;
• based at least in part on the clock signal and the indication to reset, enabling a second reset signal of the SoC after the first reset signal is enabled, wherein the second reset signal is provided to a second portion of the component of the SoC;
• and
• receiving, by the first portion of the component, the enablement of the first reset signal before the second portion of the component receives the enablement of the second reset signal.

An electronic device, comprising:

• a functional component of a System-On-a-Chip (SoC);
• a first reset generation component configured to generate a first reset signal and to enable the first reset signal based at least in part upon an indication to reset;
• and
• a second reset generation component configured to generate a second reset signal, and to synchronously enable the second reset signal after the first reset signal is enabled, wherein the first reset signal and the second reset signal are both provided to different portions of the functional component of the SoC to provide a reset enablement to the different portions at different times.