Clock distribution network, and semiconductor device and semiconductor system including the clock distribution network
AssigneeSK hynix Inc.
InventorJi Hyo KANG
Life of this patent
Estimating the term…
Abstract
A clock distribution network includes a global clock generation circuit and a data clock generation circuit. The global clock generation circuit generates a first group of division clock signals by dividing a system clock signal, and generates a second group of division clock signals by dividing the first group of division clock signals. The data clock generation circuit generates a first group of data clock signals based on the system clock signal and at least some of the first group of division clock signals, and generates a second group of data clock signals based on at least some of the first group of data clock signals and at least some of the second group of division clock signals.
Claims18
A clock distribution network comprising:
- a global clock generation circuit configured to divide a system clock signal to generate a first group of division clock signals, and to divide at least some of the first group of division clock signals to generate a second group of division clock signals;
- and
- a data clock generation circuit configured to generate a first group of data clock signals based on at least some of the first group of division clock signals and the system clock signal, and to generate a second group of data clock signals based on at least some of the second group of division clock signals and at least some of the first group of data clock signals.
A semiconductor device comprising:
- a global clock generation circuit configured to divide a system clock signal to generate a first group of division clock signals, and to divide at least some of the first group of division clock signals to generate a second group of division clock signals;
- a command address reception circuit configured to receive a command address signal and to latch the command address signal based on a command clock signal that is generated based on the second group of division clock signals;
- and
- a data clock generation circuit configured to generate a first group of data clock signals based on at least some of the first group of division clock signals and the system clock signal, and to generate a second group of data clock signals based on at least some of the second group of division clock signals and at least some of the first group of data clock signals.
A semiconductor device comprising a clock distribution network, wherein the clock distribution network comprises:
- a global clock generation circuit configured to divide a system clock signal to generate a first group of division clock signals, and to divide at least some of the first group of division clock signals to generate a second group of division clock signals;
- a phase adjustment circuit configured to generate one of the first group of division clock signals as a first reference clock signal and generate one of the second group of division clock signals as a second reference clock signal, by detecting phases of the second group of division clock signals;
- and
- a data clock generation circuit configured to generate a first group of data clock signals based on the first reference clock signal and the system clock signal and to generate a second group of data clock signals based on the second reference clock signal and at least some of the first group of data clock signals.
Dependencies are inferred from the claim text.