Quasi-asynchronous sampling frequency grid

A navigation receiver comprising:

• a plurality of RF paths configured to receive GNSS signals;
• a phase-locked loop configured to generate a clock signal;
• a plurality of clock dividers configured to receive the clock signal and to divide the clock signal;
• a plurality of navigation systems, each of the plurality of navigation systems receiving a clock signal from one of the plurality of clock dividers, each of the plurality of navigation systems works own CLKnav and comprising:
• a plurality of analog to digital convertors (ADCs) each configured to receive a GNSS signals from a respective one of the plurality of RF paths and generate a digitized signal;
• a plurality of signal processors configured to process the digitized signals;
• a plurality of decimators configured to decimate the digitized signals;
• a plurality of signal processors configured to process the decimated signals;
• a plurality of re-quantizers configured to convert the processed decimated signals into low-bit data;
• a plurality of Navigation system to CPU System (NS2CS) interface blocks configured to generate packages of a pre-set size, based on the low-bit data;
• a MUX interconnect configured to distribute data streams;
• and
• a time control unit configured to generate a tick signal is a time scale;
• a CPU system operating based on the tick signal, each navigation system in communication with the CPU system, the CPU system works CLKcpu and comprising:
• a memory configured to store data and the packages;
• a multi-channel navigation direct memory access (multi-channel navigation DMA) configured to convert the packages into data;
• a plurality of hardware accelerators configured to process the packages;
• a plurality of channels configured to process data received from the multi-channel navigation DMA;
• and
• a CPU configured to control the plurality of navigation systems and the CPU system and configured to process data received from the plurality of channels, wherein
• the CPU is configured to synchronize control between the plurality of decimators, the plurality of signal processors, the plurality of re-quantizers, the plurality of NS2CS interface blocks, the plurality of hardware accelerators, the plurality of channels and the multi-channel navigation DMA.