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US 2024/0192271 A1Published application
Design For Test For Source Synchronous Interfaces
AssigneeNXP B.V.
InventorsAkhil Garg, Sahil Jain, Abhishek Mahajan, Amit Jindal
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Abstract
A method for Design For Test (DFT) for Source Synchronous Interfaces (SSI) includes shifting a test vector into a master register slice with a DFT clock. A functional clock is generated. The test vector and the functional clock are launched from a first SSI of the master register slice. The test vector and the functional clock are captured with a second SSI of a slave. The test vector is shifted out of the slave with the DFT clock.
Claims20
A method for Design For Test (DFT) for Source Synchronous Interfaces (SSI) comprising:
- shifting a test vector into a master register slice with a DFT clock;
- generating a functional clock;
- launching the test vector and the functional clock from a first SSI of the master register slice;
- capturing the test vector and the functional clock with a second SSI of a slave;
- and
- shifting the test vector out of the slave with the DFT clock.
3 more elements
An apparatus comprising:
- a master register slice comprising a first Source Synchronous Interface (SSI);
- a slave comprising a second SSI, wherein the second SSI is configured to receive a test vector and a functional clock from the first SSI during a capture mode;
- and
- a multiplexer connected to the functional clock, a Design For Test (DFT) clock and a clock input of the slave, wherein the multiplexer is configured to select the DFT clock in response to a request to shift out the test vector from the slave and to select the functional clock during the capture mode.
1 more element
An apparatus comprising:
- a first subsystem comprising a first register comprising a first Source Synchronous Interface (SSI);
- a second subsystem comprising a second register comprising a second SSI, wherein the second SSI is configured to receive a test vector and a functional clock from the first SSI during a capture mode;
- and
- a multiplexer connected to the functional clock, a Design For Test (DFT) clock and a clock input of the second register, wherein the multiplexer is configured to select the DFT clock in response to a request to shift out the test vector from the second register and to select the functional clock during the capture mode.
1 more element
Dependencies are inferred from the claim text.