Methods for wafer bonding
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChien-Wei CHANG, Ya-Jen SHEUH, Ren-Dou LEE, Yi-Chih CHANG, Yi-Hsun CHIU, Yuan-Hsin CHI
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Abstract
Methods for improving wafer bonding performance are disclosed herein. In some embodiments, a method for bonding a pair of semiconductor substrates is disclosed. The method includes: processing at least one of the pair of semiconductor substrates, and bonding the pair of semiconductor substrates together. Each of the pair of semiconductor substrates is processed by: performing at least one chemical vapor deposition (CVD), and performing at least one chemical mechanical polishing (CMP). One of the at least one CVD is performed after all CMP performed before bonding.
Claims20
A method comprising:
- predetermining a first target surface roughness value and a second target surface roughness value associated with a first semiconductor substrate, wherein the second target surface roughness value is at least twice as large as the first target surface roughness value;
- repeating a cycle of performing chemical vapor deposition (CVD) of a dielectric material to form a dielectric layer on a top surface of the first semiconductor substrate followed by chemical mechanical polishing (CMP) on the top surface of the first semiconductor substrate when a roughness of the top surface is larger than or equal to the second target surface roughness value;
- and
- performing an additional CVD of the dielectric material on the top surface of the dielectric layer when the roughness of the top surface is smaller than the second target surface roughness value and larger than or equal to the first target surface roughness value.
A method comprising:
- predetermining a first target surface roughness value and a second target surface roughness value associated with a first semiconductor substrate, wherein the second target surface roughness value is at least twice as large as the first target surface roughness value;
- measuring a first surface roughness value of the first semiconductor substrate;
- repeating a cycle of performing chemical vapor deposition (CVD) of a dielectric material to form a first dielectric layer on a top surface of the first semiconductor substrate followed by chemical mechanical polishing (CMP) on the top surface of the first semiconductor substrate when a roughness of the top surface is larger than or equal to the second target surface roughness value;
- and
- performing an additional CVD of the dielectric material on the top surface of the first dielectric layer when the roughness of the top surface is smaller than the second target surface roughness value and larger than or equal to the first target surface roughness value, wherein the first dielectric layer is in direct contact with the first semiconductor substrate
A method comprising:
- predetermining a first target surface roughness value and a second target surface roughness value associated with a complementary metal oxide semiconductor (CMOS) wafer, wherein the second target surface roughness value is at least twice as large as the first target surface roughness value;
- repeating a cycle of performing chemical vapor deposition (CVD) of a dielectric material on a top surface of the CMOS wafer followed by chemical mechanical polishing (CMP) on the top surface of the CMOS wafer when a roughness of the top surface is larger than or equal to the second target surface roughness value, wherein the dielectric material is in direct contact with the first semiconductor substrate;
- and
- performing an additional CVD of the dielectric material on the top surface of the CMOS wafer when the roughness of the top surface is smaller than the second target surface roughness value and larger than or equal to the first target surface roughness value;
- and
- bonding the CMOS wafer to an additional wafer when the roughness of the top surface is smaller than the first target surface roughness value.
Dependencies are inferred from the claim text.