Three-dimensional memory array formation techniques

An apparatus, comprising:

• a substrate;
• a stack of materials over the substrate and comprising a plurality of levels of memory cells;
• an array of pillars over the substrate and extending at least partially through the stack of materials in a first direction non-parallel to the substrate, the array of pillars configured to provide structural support to the plurality of levels of memory cells, the array of pillars arranged in columns of pillars extending in a second direction parallel to the substrate and rows of pillars extending in a third direction parallel to the substrate;
• and
• a dielectric material located in a slit through the stack of materials and extending in the second direction, a first portion of the slit through a first portion of the stack of materials having a first width and a second portion of the slit through a second portion of the stack of materials having a second width, the dielectric material having the first width at the first portion of the slit and the second width at the second portion of the slit.

An apparatus, comprising:

• an array of first pillars extending through a plurality of levels of memory cells, each first pillar configured to couple with one or more memory cells at each level of the plurality of levels of memory cells;
• an array of second pillars associated with providing structural support for the array of first pillars, the array of second pillars arranged in columns of second pillars extending in a first direction and rows of second pillars extending in a second direction;
• and
• a dielectric material located adjacent to the array of first pillars and the array of second pillars and extending in the first direction, a first width of a first portion the dielectric material that is adjacent to the array of first pillars being less than a second width of a second portion of the dielectric material that is adjacent to the array of second pillars.