Successive approximation register analog-to-digital converter with multiple sample capacitors

A method comprising, in a successive approximation register analog-to-digital converter (SAR ADC) having a capacitor network comprising a plurality of sampling capacitors including at least a first sampling capacitor and a second sampling capacitor for sampling an analog input signal to the SAR ADC and at least one non-sampling capacitor:

• sampling, with the plurality of sampling capacitors, an analog input signal to the SAR ADC;
• comparing the sampled analog input signal of the SAR ADC to an output of a digital-to-analog converter (DAC);
• responsive to comparing the sampled analog input signal to the output of the DAC, communicating, with a successive approximation register (SAR) to the DAC successive approximations of a digital code corresponding to the sampled analog input signal;
• and
• operating the capacitor network in a plurality of phases comprising:
• a sampling phase in which the capacitor network samples the analog input signal using the plurality of sampling capacitors in a plurality of sampling sub-phases comprising:
• a first sampling sub-phase in which the first sampling capacitor samples the analog input;
• and
• a second sampling sub-phase in which the second sampling capacitor samples the analog input;
• and
• a conversion phase in which the first sampling capacitor and the second sampling capacitor are combined and charge shared and in which the capacitor network converts, using successive approximation, a sampled analog input signal sampled during the sampling phase into an equivalent digital output signal.

A system comprising:

• an analog front end configured to generate an analog input signal;
• and
• a successive approximation register analog-to-digital converter (SAR ADC) configured to convert the analog input signal to an equivalent digital signal comprising:
• a capacitor network comprising a plurality of sampling capacitors including at least a first sampling capacitor and a second sampling capacitor for sampling an analog input signal to the SAR ADC and at least one non-sampling capacitor;
• a digital-to-analog converter (DAC);
• an analog comparator configured to compare a sampled analog input signal of the SAR ADC to an output of the DAC;
• and
• a successive approximation register (SAR) configured to, responsive to an output of the analog comparator, communicate to the DAC successive approximations of a digital code corresponding to the sampled analog input signal;
• wherein the capacitor network is configured to operate in a plurality of phases comprising:
• a sampling phase in which the capacitor network samples the analog input signal using the plurality of sampling capacitors in a plurality of sampling sub-phases comprising:
• a first sampling sub-phase in which the first sampling capacitor samples the analog input;
• and
• a second sampling sub-phase in which the second sampling capacitor samples the analog input;
• and
• a conversion phase in which the first sampling capacitor and the second sampling capacitor are combined and charge shared and in which the capacitor network converts, using successive approximation, a sampled analog input signal sampled during the sampling phase into an equivalent digital output signal.