Method and apparatus for clock and data alignment that reduces power consumption

A method for pipelining phase rotators, comprising:

• implementing a first stage comprising a first number of phase rotators in parallel generating respective clock phases offset by a fixed amount;
• implementing a second stage comprising a second number of phase rotators receiving outputs from the first number of phase rotators of the first stage, the second stage outputting a first weighted sum of respective clock phases generated by the second number of phase rotators;
• wherein the second number of phase rotators is less than the first number of phase rotators, and
• wherein a total number of bits dedicated to phase selection is split across the first stage and the second stage.

A phase rotator-based Clock-and-Data Recovery (CDR) loop, comprising:

• a data sampler that samples incoming data;
• a phase detector that receives the sampled data from the data sampler and detects whether the data is sampled at an optimal point and passes the detected result to a loop filter;
• a loop filter that receives the detected result from the phase detector and outputs a code based on the detected result to instruct a phase rotator by how many codes it must rotate to sample the data at the optimal point;
• a phase rotator that receives the code from the loop filter and instructs the data sampler to sample the data, wherein
• a Finite Impulse Response (FIR) filter is interposed between the phase detector and the data sampler.