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US 2024/0187006 A1Published application
Pll circuit and transmission system
AssigneeNuvoton Technology Corporation Japan
InventorsMayuko FUJITA, Akinori SHIMMYO
Life of this patent
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Abstract
A phase-locked loop (PLL) circuit generates an output clock signal and includes: a selection circuit that selects one of a plurality of clock signals as a reference clock signal of the PLL circuit; and a control circuit that when a switch is made for the selection of the reference clock signal, temporarily reduces a division ratio used by a frequency divider that generates a feedback clock signal to be compared with the reference clock signal.
Claims11
A phase-locked loop (PLL) circuit that generates an output clock signal, the PLL circuit comprising:
- a selection circuit that selects one of a plurality of clock signals as a reference clock signal of the PLL circuit;
- and
- a control circuit that when a switch is made for the selection of the reference clock signal, temporarily reduces a division ratio used by a frequency divider that generates a feedback clock signal to be compared with the reference clock signal.
A phase-locked loop (PLL) circuit comprising:
- an oscillator that generates an output clock signal;
- a frequency divider that divides a frequency of the output clock signal;
- a phase comparator that detects a phase difference between a reference clock signal and a feedback clock signal output from the frequency divider;
- a filter circuit that outputs, to the oscillator, a control signal in accordance with the phase difference detected;
- a selection circuit that selects and outputs, as the reference clock signal, one of a plurality of clock signals to the phase comparator;
- and
- a control circuit that when a switch is made for the selection of the reference clock signal, temporarily reduces a division ratio used by the frequency divider.
4 more elements
Dependencies are inferred from the claim text.