Semiconductor device

A semiconductor device comprising:

• a first delay circuit configured to adjust a falling edge of a first clock signal;
• a second delay circuit configured to adjust a rising edge and a falling edge of a second clock signal having a phase different from a phase of the first clock signal;
• a first phase splitter configured to receive the first clock signal from the first delay circuit and to output the first clock signal and a first complementary clock signal, which is a complementary signal of the first clock signal;
• a second phase splitter configured to receive the second clock signal from the second delay circuit and to output the second clock signal and a second complementary clock signal, which is a complementary signal of the second clock signal;
• and
• a first code generator and a second code generator that are configured to receive a portion of the first clock signal, the first complementary clock signal, the second clock signal, the second complementary clock signal, and to output phase codes to at least one of the first delay circuit and the second delay circuit.

A semiconductor device comprising:

• a phase splitter configured to output a plurality of clock signals having different phases using a plurality of external clock signals having different phases;
• a plurality of code generators configured to receive a pair of selection clock signals determined from the plurality of clock signals, and to output a phase code corresponding to a phase difference error between the pair of selection clock signals;
• and
• a delay circuit configured to adjust at least at least partly simultaneously two of a rising edge and a falling edge of each of the plurality of external clock signals with reference to the phase code during a lock time.