Double-gate four-terminal semiconductor component with fin-type channel region

A metal-oxide semiconductor logic circuit, comprising

• at least one p-channel or n-channel double-gate four-terminal semiconductor component, wherein the double-gate four-terminal semiconductor component comprises:
• a substrate;
• an electrically insulating cover layer on the substrate;
• a fin-type channel region situated above the substrate and composed of a doped semiconductor material of a first conductivity type having two mutually opposite longitudinal sides extending along a longitudinal direction of the channel region, the channel region having a first end and a second end in the longitudinal direction;
• a first and a second gate electrode, which are situated on the cover layer and are arranged opposite one another each on one of the longitudinal sides of the channel region and are each electrically insulated from the longitudinal sides by an insulation layer;
• a first and a second contact region situated on the cover layer and composed of a semiconductor material of a second conductivity type, which are each arranged next to one of the gate electrodes toward the first end in the longitudinal direction of the channel region, each of the two contact regions being electrically conductively connected to the channel region and being electrically insulated from the adjacent gate electrode by an insulation layer, and
• a third and a fourth contact region situated on the cover layer and composed of a semiconductor material of the second conductivity type, which are each arranged next to one of the gate electrodes toward the second end in the longitudinal direction of the channel region, each of the two contact regions beings electrically conductively connected to the channel region and being electrically insulated from the adjacent gate electrode by an insulation layer, wherein
• a transverse extend of the channel region in a transverse direction is dimensioned such that in a first operating state, in which a first and a second operating voltage are respectively applied to the gate electrodes, two conductivity channels of the second conductivity type separated by a barrier region in the transverse direction of the channel region are formed,
• the first end of the channel region is a source end and the first and second contact region are source contact regions;
• the second end of the channel region is a drain end and the third and fourth contact regions are drain contact regions.