Integrated circuit device including a lateral diffused metal oxide semiconductor

An integrated circuit device comprising:

• a semiconductor substrate including a fin-type active region protruding in a vertical direction;
• a first conductivity type well and a second conductivity type well arranged in a first horizontal direction and in a portion of the semiconductor substrate that includes the fin-type active region;
• a source region formed in the second conductivity type well;
• a drain region formed in the first conductivity type well;
• a recess insulating layer disposed between the source region and the drain region, and including an upper insulating unit and a lower insulating unit, wherein the upper insulating unit extends from an upper surface of the first conductivity type well and into the first conductivity type well, and fills an upper substrate recess having a first length in the first horizontal direction, and wherein the lower insulating unit extends from a bottom surface of the upper substrate recess and into the first conductivity type well, and fills a lower substrate recess having a second length that is less than the first length in the first horizontal direction;
• and
• a gate electrode layer disposed between the source region and the recess insulating layer, and arranged on the first conductivity type well and the second conductivity type well, wherein the gate electrode layer covers an upper surface and side surfaces of the fin-type active region,
• wherein the recess insulating layer has a shape in which both sides thereof are asymmetric with respect to a center of the upper insulating unit.

An integrated circuit device comprising:

• a semiconductor substrate including a fin-type active region protruding in a first direction;
• a first conductivity type well and a second conductivity type well arranged in a second direction and in a portion of the semiconductor substrate that includes the fin-type active region;
• a source region formed in the second conductivity type well;
• a drain region formed in the first conductivity type well;
• a recess insulating layer disposed between the source region and the drain region, and including an upper insulating unit and a lower insulating unit, wherein the upper insulating unit extends from an upper surface of the first conductivity type well and into the first conductivity type well, and fills an upper substrate recess having a first length in the second direction, and wherein the lower insulating unit extends from a bottom surface of the upper substrate recess and into the first conductivity type well, and fills a lower substrate recess having a second length that is less than the first length in the second direction;
• a gate electrode layer disposed between the source region and the recess insulating layer, and arranged on the first conductivity type well and the second conductivity type well, wherein the gate electrode layer covers an upper surface and side surfaces of the fin-type active region;
• and
• a gate insulating layer arranged between the gate electrode layer and the first conductivity type well, and between the gate electrode layer and the second conductivity type well,
• wherein the lower insulating unit is more shifted toward the source region with respect to a center of the upper insulating unit in the second direction than to the drain region, and one side of the upper insulating unit, which faces the source region, and one side of the lower insulating unit are spaced apart from each other, and
• wherein the recess insulating layer has a shape in which both sides thereof are asymmetric with respect to the center of the upper insulating unit.