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US 2024/0186375 A1Published application
Vertical transistor with reduced cell height
AssigneeInternational Business Machines Corporation
InventorsBrent A. Anderson, Ruilong Xie, Albert M. Chu, Hemanth Jagannathan, Junli Wang
Life of this patent
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Abstract
A semiconductor structure including a vertical semiconductor channel region, a bottom source drain region arranged on a substrate at a bottom of the vertical semiconductor channel region, a metal gate disposed around the vertical semiconductor channel region, where a first portion of the metal gate extends above the vertical semiconductor channel region, and a gate contact entirely above the vertical semiconductor channel region.
Claims20
A semiconductor structure comprising:
- a vertical semiconductor channel region;
- a bottom source drain region arranged on a substrate at a bottom of the vertical semiconductor channel region;
- a metal gate disposed around the vertical semiconductor channel region, wherein a first portion of the metal gate extends above the vertical semiconductor channel region;
- and
- a gate contact entirely above the vertical semiconductor channel region.
2 more elements
A semiconductor structure comprising:
- a vertical semiconductor channel region;
- a bottom source drain region arranged on a substrate at a bottom of the vertical semiconductor channel region;
- a metal gate disposed around the vertical semiconductor channel region;
- and
- a top source drain region above the vertical semiconductor channel region, wherein a topmost surface of the metal gate is substantially flush with a topmost surface of the top source drain.
2 more elements
A semiconductor structure comprising:
- two vertical semiconductor channel regions aligned and arrange end-to-end;
- a bottom source drain region arranged on a substrate at a bottom of each of two the vertical semiconductor channel regions;
- a metal gate disposed around the two vertical semiconductor channel regions, wherein a first portion of the metal gate situated between the two vertical semiconductor channel regions extends above the two vertical semiconductor channel regions;
- and
- a single gate contact entirely above the vertical semiconductor channel regions.
2 more elements
Dependencies are inferred from the claim text.