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US 2024/0186293 A1Published application
Semiconductor package having chip stack
AssigneeSamsung Electronics Co., Ltd.
InventorWon-young KIM
Life of this patent
Estimating the term…
Abstract
A semiconductor package includes a substrate, a master chip on the substrate, a first slave chip on a top surface of the master chip and partially exposing the top surface of the master chip, the first slave chip having a same size as the master chip and having a same storage capacity as the master chip, and a first chip connector on the exposed top surface of the master chip and coupled to the master chip and the first slave chip.
Claims20
A semiconductor package, comprising:
- a substrate;
- a first semiconductor chip on the substrate, the first semiconductor chip having a first region and a second region in a plan view;
- a second semiconductor chip on a top surface of the second region of the first semiconductor chip, the second semiconductor chip exposing the first region and completely covering the second region;
- a first signal connector on a top surface of the first region of the first semiconductor chip, the first signal connector being coupled to the first semiconductor chip and the substrate;
- a second signal connector on the top surface of the first region of the first semiconductor chip, the second signal connector being coupled to the second semiconductor chip and the first semiconductor chip;
- a third connector for power or ground on the top surface of the second region of the first semiconductor chip, the third connector being coupled to the substrate;
- and
- an insulation pattern on the substrate and covering a side surface of the first semiconductor chip,
- wherein each of the first signal connector and the third connector includes a wiring line pattern, and
- wherein the first signal connector and the third connector cover a part of the insulation pattern.
7 more elements
A semiconductor package, comprising:
- a substrate;
- a master chip on the substrate, the master chip including a first region, a second region, and a third region;
- a first slave chip on the second region of the master chip and exposing the first region and the third region of the master chip;
- a first chip connector on the first region and the third region of the master chip and coupled to the master chip and the first slave chip;
- a connector for power or ground on the second region of the master chip and coupled to the master chip and the substrate;
- and
- a signal connector on the first region and the third region of the master chip, the signal connector being electrically connected to the substrate and the master chip,
- wherein the first region is in located in a first direction of the first slave chip, and
- wherein the third region is in located in a second direction, which is perpendicular to the first direction, of the first slave chip.
6 more elements
Dependencies are inferred from the claim text.