Semiconductor system
AssigneeSK hynix Inc.
InventorsKang Sub KWAK, Sang Sic YOON
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a driving signal generation circuit configured to generate a pull-up driving signal that is enabled when a data clock input control signal is input during a normal operation, configured to generate a pull-down driving signal that is enabled when any one of a write signal and a read signal is input, and configured to generate the pull-down driving signal that is enabled after a set interval when a synchronization signal is input, and a sync enable signal generation circuit configured to generate a sync enable signal for receiving a data clock from a time at which the pull-up driving signal is enabled to a time at which the pull-down driving signal is enabled.
Claims37
A semiconductor device comprising:
- a driving signal generation circuit configured to generate a pull-up driving signal that is enabled when a data clock input control signal is input during a normal operation, configured to generate a pull-down driving signal that is enabled when any one of a write signal and a read signal is input, and configured to generate the pull-down driving signal that is enabled after a set interval when a synchronization signal is input;
- and
- a sync enable signal generation circuit configured to generate a sync enable signal, for receiving a data clock, from a time at which the pull-up driving signal is enabled to a time at which the pull-down driving signal is enabled.
A semiconductor device comprising:
- a driving signal generation circuit configured to generate a pull-up driving signal that is enabled when a data clock input control signal is input during a normal operation, configured to generate a pull-down driving signal that is enabled when any one of a write signal and a read signal is input, and configured to block an input of the write signal and the read signal when a synchronization signal is input;
- and
- a sync enable signal generation circuit configured to generate a sync enable signal, for receiving a data clock, from a time at which the pull-up driving signal is enabled to a time at which the pull-down driving signal is enabled.
A semiconductor device comprising:
- a driving signal generation circuit configured to generate a pull-up driving signal that is enabled when a data clock input control signal is input during a normal operation and configured to generate a pull-down driving signal that is enabled when any one of a write signal, a read signal, and a synchronization signal is input;
- and
- a sync enable signal generation circuit configured to generate a sync enable signal for receiving a data clock from a time at which the pull-up driving signal is enabled to a time at which the pull-down driving signal is enabled.
A semiconductor device comprising:
- a driving signal generation circuit configured to generate a pull-up driving signal that is enabled when a data clock input control signal is input during a normal operation, configured to generate a pull-down driving signal that is enabled based on a write signal, a read signal, and a flag signal, and configured to delay timing at which the pull-down driving signal is enabled when the flag signal is enabled;
- and
- a sync enable signal generation circuit configured to generate a sync enable signal for receiving a data clock from a time at which the pull-up driving signal is enabled to a time at which the pull-down driving signal is enabled.
A semiconductor device comprising:
- a control circuit configured to generate a sync enable signal that is enabled during an interval of a write operation and a read operation during a normal operation and configured to extend an interval in which the sync enable signal is enabled when a synchronization signal is input before the write operation and the read operation are completed;
- and
- a data clock input circuit configured to receive a data clock during the interval in which the sync enable signal is enabled and configured to generate first to fourth internal clocks by dividing a frequency of the data clock that has been received.
A semiconductor system comprising:
- a controller configured to output a command address and a data clock and configured to input and output data;
- a first memory device configured to input and output the data in synchronization with the data clock when performing a normal operation based on the command address;
- and
- a second memory device configured to perform a data clock extension operation of extending an interval in which the data clock is received based on the command address when the first memory device performs the normal operation.
Dependencies are inferred from the claim text.