Display driver integrated circuit, system-on-chip, and display system including the system-on-chip

A System-on-Chip (SoC) comprising:

• a clock generator configured to generate an internal operating clock;
• and
• a control circuit configured to generate and output the frame data based on the internal operating clock,
• wherein the control circuit is further configured to:
• transmit first frame data, which is generated based on the internal operating clock, to a display panel,
• receive a sync request signal from the display panel, and
• transmit a frequency signal to the display panel based on the internal operating clock, in response to the sync request signal.

A display system comprising:

• a System-on-Chip (SoC) configured to:
• generate, based on a first internal operating clock, frame data, and
• output the frame data;
• and
• a display panel configured to output, based on a second internal operating clock, an image corresponding to the frame data,
• wherein the display panel is further configured to, in a frame data update period when an update of the frame data is performed:
• receive first frame data from the SoC,
• perform a first synchronization operation, which synchronizes the second internal operating clock with the first internal operating clock, based on the first frame data, and
• output the image corresponding to the first frame data, and
• wherein the display panel is further configured to, in a low power mode (LPM) period when the update of the frame data is not performed:
• transmit a sync request signal to the SoC based on a result of monitoring a state of the display panel,
• receive a frequency signal, which is generated based on the first internal operating clock, from the SoC in response to the sync request signal, and
• perform a second synchronization operation, which synchronizes the second internal operating clock with the first internal operating clock, based on the frequency signal.