Stochastic computing method and circuit, chip and device

A stochastic computing circuit, comprising a control circuit, a pulse output circuit and a computing circuit, wherein both the control circuit and the computing circuit are connected to the pulse output circuit;

• the control circuit is configured to input a control parameter into the pulse output circuit, the control parameter comprising a control word having an integer part and a decimal part;
• the pulse output circuit is configured to input a pulse to be computed into the computing circuit according to the control parameter and multiple reference pulses having evenly spaced phases, the pulse to be computed comprising at least one of a first sub-pulse and a second sub-pulse which are distributed in a time domain, a period of the first sub-pulse and a period of the second sub-pulse being controlled by the integer part, and probabilities that the first sub-pulse and the second sub-pulse appear in the pulse to be computed being controlled by the decimal part;
• and
• the computing circuit is configured to perform logic computing according to a duty cycle of the pulse to be computed and output a computing result of the logic computing.