Circuits And Methods For Receiving Data Signals Having Different Common-Mode Voltages
AssigneeAltera Corporation
InventorChee Hong Aw
Life of this patent
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Abstract
A receiver circuit includes a first sense amplifier circuit that generates a first data signal based on a second data signal that has a first common-mode voltage during a first mode of operation. The receiver circuit includes a second sense amplifier circuit that generates a third data signal based on a fourth data signal that has a second common-mode voltage less than the first common-mode voltage during a second mode of operation. The receiver circuit includes a switch circuit that provides first data bits indicated by the first data signal to an output during the first mode of operation. The switch circuit provides second data bits indicated by the third data signal to the output during the second mode of operation.
Claims20
A receiver circuit comprising:
- a first sense amplifier circuit that generates a first data signal based on a second data signal that has a first common-mode voltage during a first mode of operation;
- a second sense amplifier circuit that generates a third data signal based on a fourth data signal that has a second common-mode voltage that is less than the first common-mode voltage during a second mode of operation;
- and
- a switch circuit that provides first data bits indicated by the first data signal to an output during the first mode of operation, wherein the switch circuit provides second data bits indicated by the third data signal to the output during the second mode of operation.
A method for resolving data using a receiver circuit, the method comprising:
- generating a first data signal based on a second data signal having a first common-mode voltage using a first latch circuit in the receiver circuit during a first mode of operation;
- providing first bits indicated by the first data signal to an output using a switch circuit in the receiver circuit during the first mode of operation;
- generating a third data signal based on a fourth data signal having a second common-mode voltage that is less than the first common-mode voltage using a second latch circuit in the receiver circuit during a second mode of operation;
- and
- providing second bits indicated by the third data signal to the output using the switch circuit during the second mode of operation.
An integrated circuit comprising a receiver circuit, wherein the receiver circuit comprises:
- a first sense amplifier latch circuit that outputs first data bits based on a first input signal that comprises a first common-mode voltage when the first sense amplifier latch circuit is enabled;
- a second sense amplifier latch circuit that outputs second data bits based on a second input signal that comprises a second common-mode voltage when the second sense amplifier latch circuit is enabled;
- and
- a multiplexer circuit that outputs the first data bits when the first sense amplifier latch circuit is enabled, wherein the multiplexer circuit outputs the second data bits when the second sense amplifier latch circuit is enabled.
Dependencies are inferred from the claim text.