Semiconductor structure and manufacturing method thereof

Abstract

Disclosed are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate, a channel layer, a barrier layer and a P-type semiconductor layer sequentially stacked in a first direction. The P-type semiconductor layer includes a high-resistance passivation region and an activation region, and the high-resistance passivation region is located on a side, away from the substrate, of the activation region. When a semiconductor device is in an off state, the activation region of the P-type semiconductor layer may deplete 2DEG at the channel to realize an enhancement-mode device. The high-resistance passivation region is passivated to form a high-resistance structure, which may reduce a gate leakage current in the off state and improve power characteristics of the semiconductor device.

Dependencies are inferred from the claim text.