Semiconductor chip and semiconductor package including the same

A semiconductor package comprising:

• a first semiconductor chip including a first semiconductor substrate having a first active surface and a first non-active surface opposite to each other, a plurality of first through electrodes passing through the first semiconductor substrate, a first front insulating layer on the first active surface, and a first rear insulating layer on the first non-active surface;
• a second semiconductor chip including a second semiconductor substrate having a second active surface and a second non-active surface opposite to each other, and a second front insulating layer on the second active surface, the second active surface facing the first non-active surface and the second semiconductor chip being stacked on the first semiconductor chip;
• and
• a plurality of first bonding pads between the first semiconductor chip and the second semiconductor chip, surrounded by the first rear insulating layer and the second front insulating layer, and electrically connected to the plurality of first through electrodes,
• wherein the second front insulating layer includes a cover insulating portion extending into the second semiconductor substrate through the second active surface and covering a side surface of the second semiconductor chip.

A semiconductor package comprising:

• a high bandwidth memory (HBM) control die including a first semiconductor substrate having a first active surface and a first non-active surface opposite to each other, a plurality of first through electrodes passing through the first semiconductor substrate, a first front insulating layer on the first active surface, and a first rear insulating layer on the first non-active surface;
• a plurality of dynamic random access memory (DRAM) dies including a second semiconductor substrate having a second active surface and a second non-active surface opposite to each other, a plurality of second through electrodes passing through the second semiconductor substrate, a second front insulating layer on the second active surface, and a second rear insulating layer on the second non-active surface, the second active surface facing the first non-active surface, and the plurality of DRAM dies being sequentially stacked on the HBM control die and having horizontal widths less than a horizontal width of the HBM control die;
• a plurality of first bonding pads between a lowermost DRAM die of the plurality of DRAM dies and the HBM control die and surrounded by the second front insulating layer of the lowermost DRAM die of the plurality of DRAM dies and the first rear insulating layer;
• and
• a plurality of second bonding pads between two adjacent DRAM dies among the plurality of DRAM dies, and surrounded by the second front insulating layer and the second rear insulating layer between the two adjacent DRAM dies among the plurality of DRAM dies,
• wherein the second front insulating layer includes a cover insulating portion extending into the second semiconductor substrate through the second active surface and covering a side surface of each of the DRAM dies, and only the cover insulating portion, the second semiconductor substrate, and the second rear insulating layer are exposed at the side surface of each of the DRAM dies.