Chip package structure and chip structure

A chip package structure, comprising:

• a wiring substrate comprising a first conductive pad;
• and
• a chip structure over the wiring substrate, wherein the chip structure comprises:
• a substrate;
• an interconnect layer under the substrate;
• a second conductive pad under the interconnect layer;
• and
• a conductive bump connected between the first conductive pad and the second conductive pad, wherein
• a first center portion of the first conductive pad is misaligned with a second center portion of the second conductive pad relative to an axis perpendicular to a surface of the substrate.

A chip structure, comprising:

• a substrate;
• an interconnect layer over the substrate;
• a conductive pad over the interconnect layer;
• and
• a conductive bump over the conductive pad, wherein the conductive bump has a first portion, a second portion, and a neck portion between the first portion and the second portion, the first portion is between the neck portion and the conductive pad, the neck portion is narrower than both of the first portion and the second portion, and a first composition of the neck portion is different from a second composition of the first portion.