Chip select wiring for a dual device package

An apparatus, comprising:

• a substrate;
• a plurality of chip select signal lines located within the substrate, the plurality of chip select signal lines comprising at least a first chip select signal line and a second chip select signal line;
• a plurality of first memory devices, each first memory device of the plurality of first memory devices coupled with a first outside surface of the substrate, each first memory device comprising a first lower memory die coupled with the second chip select signal line and a first upper memory die coupled with the first chip select signal line;
• a plurality of second memory devices, each second memory device of the plurality of second memory devices coupled with a second outside surface of the substrate, each second memory device comprising a second lower memory die coupled with the first chip select signal line and a second upper memory die coupled with the second chip select signal line;
• and
• a controller coupled with the plurality of chip select signal lines and operable to:
• transmit a first chip select signal to each of the first lower memory dies and the second upper memory dies via the first chip select signal line based on identifying a first rank of memory dies to access.

A non-transitory computer-readable medium storing code for an apparatus, the code comprising instructions executable by a processor to:

• identify a first rank of memory dies to access based on receiving a first command;
• generate a first chip select signal based on identifying the first rank of memory cell;
• and
• transmit the first chip select signal to a lower memory die of a first memory device and an upper memory die of a second memory device via a first chip select signal line based on generating the first chip select signal.