Semiconductor device structure including forksheet transistors and methods of forming the same

A semiconductor device structure, comprising:

• a first dielectric wall;
• a plurality of first semiconductor layers vertically stacked and extending outwardly from a first side of the first dielectric wall;
• a second dielectric wall disposed in parallel with the first dielectric wall;
• a plurality of second semiconductor layers vertically stacked and extending outwardly from both sides of the second dielectric wall;
• a third dielectric wall disposed in parallel with the first dielectric wall;
• a plurality of third semiconductor layers vertically stacked and extending outwardly from a first side of the third dielectric wall;
• a gate structure disposed over a portion of the first, second, and third dielectric walls;
• a source/drain contact disposed over a portion of the first dielectric wall and in contact with an epitaxial source/drain feature;
• a metal on gate bridge contact disposed over the gate structure and in contact with a portion of the gate structure and the source/drain contact;
• and
• a gate bridge contact disposed over a portion of the gate structure and in contact with the second dielectric wall.

A method for forming a semiconductor device structure, comprising:

• forming first, second, third, and fourth fin structures from a substrate, wherein the first fin structure includes a first plurality of semiconductor layers, the second fin structure includes a second plurality of semiconductor layers, the third fin structure includes a third plurality of semiconductor layers, and the fourth fin structure includes a fourth plurality of semiconductor layers, and wherein each of the first, second, third, and fourth plurality of semiconductor layers comprises first semiconductor layers and second semiconductor layers;
• forming a first dielectric wall between the first fin structure and the second fin structure;
• forming a second dielectric wall between the third fin structure and the fourth fin structure;
• forming a sacrificial gate stack over a portion of the first, second, third, and fourth fin structures, and over a portion of the first and second dielectric walls;
• removing a portion of the first, second, third, and fourth fin structures not covered by the sacrificial gate stack;
• removing the sacrificial gate stack to expose portions of the first, second, third, and fourth fin structures;
• selectively removing the second semiconductor layers of the first, second, third, and fourth plurality of semiconductor layers;
• surrounding a first gate electrode layer over at least three surfaces of each of the first semiconductor layer of the third plurality of semiconductor layers, wherein the first gate electrode layer has a first conductivity type;
• surrounding a second gate electrode layer over at least three surfaces of each of the first semiconductor layer of the fourth plurality of semiconductor layers, wherein the second gate electrode layer has a second conductivity type opposite the first conductivity type;
• performing a planarization operation so that top surfaces of the first and second dielectric walls and top surfaces of the first and second gate electrode layers are substantially co-planar;
• forming a gate bridge contact on the second dielectric wall;
• and
• forming a gate via contact on the gate bridge contact.