Stacked semiconductor device test circuits and methods of use
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJen-Yuan CHANG
Life of this patent
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Abstract
A control circuit is included in a first die of a stacked semiconductor device. The first die further includes a transistor that is electrically connected to the control circuit. The transistor is configured to be controlled by the control circuit to selectively block a die-to-die interconnect. In this way, the die-to-die interconnect may be selectively blocked to isolate the first die and a second die of the stacked semiconductor device for independent testing after bonding. This may increase the effectiveness of a testing to identify and isolate defects in the first die or the second die, which may further increase the effectiveness of performing rework or repair on the stacked semiconductor device.
Claims20
A method, comprising:
- forming a first plurality of circuits on a first substrate of a first die,
- wherein the first plurality of circuits includes:
- a test circuit, and
- a control circuit;
- forming a second plurality of circuits on a second substrate of a second die;
- bonding the first die and the second die to form a stacked semiconductor device;
- and
- performing, through the test circuit and using the control circuit to selectively isolate the first die and the second die, independent circuit probe tests of a subset of the first plurality of circuits and a subset of the second plurality of circuits,
- wherein a first independent circuit probe test, of the subset of the first plurality of circuits, is performed when the first die and the second die are isolated, and
- wherein a second independent circuit probe test, of the subset of the second plurality of circuits, is performed when the first die and the second die are electrically connected.
A stacked semiconductor device, comprising:
- a first die comprising a first plurality of circuits on a first substrate,
- wherein the first plurality of circuits includes a test circuit and a control circuit;
- and
- a second die comprising a second plurality of circuits on a second substrate,
- wherein the second die is bonded to the first die,
- wherein the control circuit is configured to selectively isolate the first die and the second die, and
- wherein the test circuit is configured to:
- perform a first independent circuit probe test, of a subset of the first plurality of circuits, when the first die and the second die are isolated, and
- perform a second independent circuit probe test, of a subset of the second plurality of circuits, when the first die and the second die are electrically connected.
A method, comprising:
- forming a first plurality of circuits on a first substrate of a first die,
- wherein the first plurality of circuits includes:
- a test circuit, and
- a control circuit;
- forming a second plurality of circuits on a second substrate of a second die;
- bonding the first die and the second die to form a stacked semiconductor device;
- electrically isolating the first die from the second die;
- performing an independent test of the first die based on the first die being electrically isolated from the second die;
- electrically connecting the first die and the second die;
- and
- performing an independent test of the second die based on the first die and the second die being electrically connected.
Dependencies are inferred from the claim text.