Adjacent buried power rail for stacked field-effect transistor architecture

A method for fabricating a semiconductor device by a fabrication system, the method comprising:

• forming, by the fabrication system, a transistor region on a substrate;
• forming, by the fabrication system, an interconnect hierarchy on a top side of the transistor region;
• forming, by the fabrication system, a carrier wafer on top of the interconnect hierarchy;
• flipping, by the fabrication system, the semiconductor device onto the carrier wafer;
• removing, by the fabrication system, the substrate;
• and
• forming, by the fabrication system, two or more buried power rails within a cell.

A method for fabricating a semiconductor device by a fabrication system, the method comprising:

• stacking, by the fabrication system, a first transistor of the semiconductor device on a second transistor of the semiconductor device, wherein the first transistor is offset laterally from the second transistor;
• forming, by the fabrication system, a power rail layer comprising a first buried power rail and a second buried power rail;
• and
• coupling, by the fabrication system, the first buried power rail to the first transistor and the second buried power rail to the second transistor.