Counter-based sense amplifier method for memory cells

A memory system, comprising:

• one or more arrays of memory cells;
• one or more counters coupled with the one or more arrays of memory cells;
• and
• one or more processors coupled with the one or more arrays of memory cells and configured to cause the memory system to:
• store, at the one or more counters, a respective value corresponding to a quantity of respective memory cells of the one or more arrays of memory cells that store a first logic value;
• read, from a counter of the one or more counters, a first value corresponding to the quantity of the respective memory cells storing the first logic value;
• read, during a data reading phase, from the respective memory cells by applying a ramp of biasing voltages;
• count, during the data reading phase, a quantity of bits of the respective memory cells having the first logic value;
• and
• stop the data reading phase based at least in part on the quantity of bits having the first logic value.

A memory device, comprising:

• one or more memory arrays comprising one or more memory cells, the one or more memory arrays configured to store at least one codeword including data bits and parity bits;
• one or more counters associated with error correction bits, the one or more counters storing a respective value corresponding to a quantity of respective memory cells of the one or more memory cells that store a first logic value;
• and
• one or more processors supporting the memory device for reading the one or more memory cells.

A memory device, comprising:

• one or more arrays of memory cells;
• one or more counters associated with a respective codeword of the one or more arrays and coupled with the one or more arrays of memory cells;
• and
• one or more processors coupled with the one or more arrays of memory cells and configured to cause the memory device to:
• store, at the one or more counters, a value of a number of bits of the respective codeword having a first logic value;
• starting a counter reading phase, prior to starting a codeword reading phase, during a pre-charge phase to read a content of the one or more counters;
• and
• stopping the codeword reading phase when the number of bits having the first logic value is greater than or equal to the content of the one or more counters.