Architecture and method for nand memory operation

A method of operating a memory device comprising a first memory cell string that includes a bottom-select-gate (BSG) transistor, memory cells (MCs), and a top-select-gate (TSG) transistor that are connected in series, the memory cells including a selected memory cell and an unselected memory cell, the unselected memory cell including a first adjacent memory cell, a second adjacent memory cell and third memory cell, the selected memory cell being programmed and arranged between the first adjacent memory cell and the second adjacent memory cell, the method comprising:

• applying, in a pre-verify stage, a first verify bias voltage on a selected word line that the selected memory cell is coupled to;
• applying, in the pre-verify stage, a first bias voltage on a first word line that the third memory cell is coupled to;
• applying, in a verify stage, a second verify voltage on the selected word line;
• applying, in the verify stage, a first pass voltage on a second word line that the second adjacent memory cell is coupled to;
• applying, in the verify stage, a second pass voltage on a third word line that the first adjacent memory cell is coupled to;
• and
• applying, in the verify stage, a second bias voltage on the first word line, wherein:
• the second bias voltage is smaller than the first bias voltage;
• and at least one of the first pass voltage and the second pass voltage is larger than the second bias voltage.

An electronic system, comprising:

• a memory device, including:
• a first memory cell string that includes a bottom-select-gate (BSG) transistor, memory cells, and a top-select-gate (TSG) transistor that are connected in series, the memory cells including a selected memory cell and an unselected memory cell, the unselected memory cell including a first adjacent memory cell, a second adjacent memory cell and third memory cell, the selected memory cell being programmed and arranged between the first adjacent memory cell and the second adjacent memory cell;
• word lines coupled respectively with the memory cells;
• and
• processing circuitry coupled to the word lines and configured to:
• apply, in a pre-verify stage, a first verify voltage on a selected word line that the selected memory cell is coupled to;
• apply, in the pre-verify stage, a first bias voltage on a first word line that the third memory cell is coupled to;
• apply, in a verify stage, a second verify voltage on the selected word line;
• apply, in the verify stage, a first pass voltage on a second word line that the second adjacent memory cell is coupled to;
• apply, in the verify stage, a second pass voltage on a third word line that the first adjacent memory cell is coupled to;
• and
• apply, in the verify stage, a second bias voltage on the first word line, wherein:
• the second bias voltage is smaller than the first bias voltage;
• and at least one of the first pass voltage and the second pass voltage is larger than the second bias voltage;
• and
• a processor, coupled to the memory device and configured to send commands to the memory device.