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US 2024/0177765 A1Published application
Memory device having load offset mismatch compensation
AssigneeSamsung Electronics Co., Ltd.
InventorsMI JI JANG, YOUNG HUN SEO
Life of this patent
Estimating the term…
Abstract
A memory device including a memory cell array which includes a plurality of memory cells connected to each of a plurality of bit lines and word lines, a first bit line sense amplifier electrically connected to a first bit line through a first memory cell and a first connecting wiring and a second bit line sense amplifier electrically connected to a second bit line through a second connecting wiring having a length different from that of the first connecting wiring. A first compensation load of the first bit line and a second compensation load of the second bit line are adjusted to equalize RC loads of the first bit line and the second bit line.
Claims25
A memory device comprising:
- a memory cell array including a plurality of memory cells connected to a plurality of bit lines and a plurality of word lines;
- a first bit line sense amplifier electrically connected to a first memory cell from among the plurality of memory cells through a first bit line from among the plurality of bit lines and a first connecting wiring having a first length;
- a first offset compensation transistor electrically connected to the first bit line and the first bit line sense amplifier;
- a second bit line sense amplifier electrically connected to a second memory cell from among the plurality of memory cells through a second bit line from among the plurality of bit lines and a second connecting wiring having a second length different than the first length;
- and
- a second offset compensation transistor electrically connected to the second bit line and the second bit line sense amplifier,
- wherein the first bit line includes a first compensation load and the second bit line includes a second compensation load to equalize RC loads of the first bit line and the second bit line.
4 more elements
10-13. (canceled)
17-19. (canceled)
A memory device comprising:
- a memory cell array including a first memory cell connected between a first bit line node and a first complementary bit line node, and a second memory cell connected between a second bit line node and a second complementary bit line node;
- a first bit line sense amplifier including a first offset compensation transistor connected between the first bit line node and a first sensing bit line node, and a first complementary offset compensation transistor connected between the first complementary bit line node and a first sensing complementary bit line node;
- and
- a second bit line sense amplifier including a second offset compensation transistor connected between the second bit line node and a second sensing bit line node, and a second complementary offset compensation transistor connected between the second complementary bit line node and a second sensing complementary bit line node,
- wherein a first length of a first connecting wiring connecting the first bit line node and one end of the first offset compensation transistor is different from a second length of a second connecting wiring connecting the second bit line node and one end of the second offset compensation transistor, and
- wherein the first bit line includes a first compensation load of the first connecting wiring and the second bit line includes a second compensation load of the second connecting wiring to equalize RC loads of the first connecting wiring and the second connecting wiring.
3 more elements
24-26. (canceled)
A memory device comprising:
- a memory cell array on a first layer, and including a plurality of memory cells connected between a plurality of bit lines and a plurality of complementary bit lines that are paired;
- a first offset compensation transistor on a second layer spaced below the first layer, and having one end connected to a first sensing bit line node and an other end connected to a first bit line from among the plurality of bit lines through a first connecting wiring;
- a first complementary offset compensation transistor on the second layer, and having one end connected to a first complementary sensing bit line node and an other end connected to a first complementary bit line from among the plurality of complementary bit lines through a first complementary connecting wiring having a same length as the first connecting wiring;
- a second offset compensation transistor on the second layer, and having one end connected to a second sensing bit line node and an other end connected to a second bit line from among the plurality of bit lines through a second connecting wiring having a length different than a length of the first connecting wiring;
- and
- a second complementary offset compensation transistor on the second layer, and having one end connected to a second complementary sensing bit line node and an other end connected to a second complementary bit line from among the plurality of complementary bit lines through a second complementary wiring having a same length as the second connecting wiring,
- wherein one of channel length and channel width of the first offset compensation transistor, or one of channel lengths and channel widths of the second offset compensation transistor and the second complementary offset compensation transistor are set to adjust a first compensation load for the first connecting wiring, and a second compensation load for the second connecting wiring and the second complementary wiring, based on a length ratio of the first connecting wiring and the second connecting wiring.
4 more elements
28-31. (canceled)
(canceled)
Dependencies are inferred from the claim text.