Indication in memory system or sub-system of latency associated with performing an access command
AssigneeLodestar Licensing Group LLC
InventorsRobert Nasry Hasbun, Dean D. Gans, Sharookh Daruwalla
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AssigneeLodestar Licensing Group LLC
InventorsRobert Nasry Hasbun, Dean D. Gans, Sharookh Daruwalla
Estimating the term…
Methods, systems, and devices for a latency indication in a memory system or sub-system are described. An interface controller of a memory system may transmit an indication of a time delay (e.g., a wait signal) to a host in response to receiving an access command from the host. The interface controller may transmit such an indication when a latency associated with performing the access command is likely to be greater than a latency anticipated by the host. The interface controller may determine a time delay based on a status of buffer or a status of memory device, or both. The interface controller may use a pin designated and configured to transmit a command or control information to the host when transmitting a signal including an indication of a time delay. The interface controller may use a quantity, duration, or pattern of pulses to indicate a duration of a time delay.
A memory system, comprising:
A method, comprising:
An apparatus, comprising:
Dependencies are inferred from the claim text.