Display panel, driving circuit and display device

A display panel, comprising:

• a pixel circuit;
• and
• a light-emitting element,
• wherein:
• the pixel circuit includes a light emission control module, the light emission control module is configured to make the light-emitting element emit light under control of a light emission control signal;
• the pixel circuit includes a first pixel circuit, the first pixel circuit includes a first reset module, the light-emitting element includes a first light-emitting element that emits light of a first color, and the first reset module provides a first reset signal to the first light-emitting element under control of a first scan signal;
• a data writing cycle of the pixel circuit includes a data writing phase and m holding phases;
• in the data writing phase, the first scan signal includes at least one first valid pulse;
• the light emission control signal includes one second valid pulse in the data writing phase and in each of the holding phases;
• and
• working modes of the display panel include a first mode, wherein in the first mode, an interval between a start time of a first valid pulse in an (i+1)-th data writing cycle and an end time of a last second valid pulse in the i-th data writing cycle is t1,
• t
• ⁢
• 1
• ≥
• 1
• ⁢
• H
• ,
• H
• =
• 1
• F
• ×
• n
• ,
• n is the number of rows of pixel circuits, F is a refresh rate of the display panel in the first mode, m≥1, i≥1, and m and i are integers.

A driving circuit configured to provide signals for a display panel, the display panel comprising:

• a pixel circuit;
• and
• a light-emitting element,
• wherein:
• the pixel circuit includes a light emission control module, the light emission control module is configured to make the light-emitting element emit light under control of a light emission control signal;
• the pixel circuit includes a first pixel circuit, the first pixel circuit includes a first reset module, the light-emitting element includes a first light-emitting element that emits light of a first color, and the first reset module provides a first reset signal to the first light-emitting element under control of a first scan signal;
• a data writing cycle of the pixel circuit includes a data writing phase and m holding phases;
• in the data writing phase, the first scan signal includes at least one first valid pulse;
• the light emission control signal includes one second valid pulse in the data writing phase and in each of the holding phases;
• and
• working modes of the display panel include a first mode, wherein in the first mode, an interval between a start time of a first valid pulse in an (i+1)-th data writing cycle and an end time of a last second valid pulse in an i-th data writing cycle is t1, and in the data writing phase, a duration of the light emission control signal being an invalid pulse is t2,
• t
• ⁢
• 1
• t
• ⁢
• 2
• ≥
• 1
• ⁢
• %
• ,
• and
• /
• or
• ,
• t
• ⁢
• 1
• ≥
• H
• ,
• H
• =
• 1
• F
• ×
• n
• ,
• n is the number of rows of pixel circuits, F is a refresh rate of the display panel in the first mode, m≥1, i≥1, and m and i are integers.

A display device including a display panel, the display panel comprising:

• a pixel circuit;
• and
• a light-emitting element,
• wherein:
• the pixel circuit includes a light emission control module, the light emission control module is configured to make the light-emitting element emit light under control of a light emission control signal;
• the pixel circuit includes a first pixel circuit, the first pixel circuit includes a first reset module, the light-emitting element includes a first light-emitting element that emits light of a first color, and the first reset module provides a first reset signal to the first light-emitting element under control of a first scan signal;
• a data writing cycle of the pixel circuit includes a data writing phase and m holding phases;
• in the data writing phase, the first scan signal includes at least one first valid pulse;
• the light emission control signal includes one second valid pulse in the data writing phase and in each of the holding phases;
• and
• working modes of the display panel include a first mode, wherein in the first mode, an interval between a start time of a first valid pulse in an (i+1)-th data writing cycle and an end time of a last second valid pulse in an i-th data writing cycle is t1, and in the data writing phase, a duration of the light emission control signal being an invalid pulse is t2,
• t
• ⁢
• 1
• t
• ⁢
• 2
• ≥
• 1
• ⁢
• %
• ,
• and
• /
• or
• ,
• t
• ⁢
• 1
• ≥
• H
• ,
• H
• =
• 1
• F
• ×
• n
• ,
• n is the number of rows of pixel circuits, F is a refresh rate of the display panel in the first mode, m≥1, i≥1, and m and i are integers.