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US 2024/0176945 A1Published application
Hard-to-fix (htf) design rule check (drc) violations prediction
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChing Hsu, Shih-Yao Lin, Yi-Lin Chuang
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Abstract
A method includes: training a machine learning model with a plurality of electronic circuit placement layouts; predicting, by the machine learning model, fix rates of design rule check (DRC) violations of a new electronic circuit placement layout; identifying hard-to-fix (HTF) DRC violations among the DRC violations based on the fix rates of the DRC violations of the new electronic circuit placement layout; and fixing, by an engineering change order (ECO) tool, the DRC violations.
Claims20
A system, comprising:
- a hard-to-fix (HTF) design rule check (DRC) violation prediction platform comprising a memory and a processor, wherein the memory is configured to store data and processing instructions, and wherein the processor is configured to execute the processing instructions to cause the HTF DRC violation prediction platform to:
- train a machine learning model with a plurality of electronic circuit placement layouts, wherein to train the machine learning model with the plurality of electronic circuit placement layouts the processor is configured to execute the processing instructions to cause the HTF DRC violation prediction platform to:
- extract a plurality of feature combinations of the plurality of electronic circuit placement layouts;
- calculate fix rates of DRC violations present on the plurality of electronic circuit placement layouts;
- establish a relationship between the fix rates and the plurality of feature combinations;
- and
- normalize the plurality of feature combinations of the plurality of electronic circuit placement layouts;
- predict, by the machine learning model, fix rates of DRC violations of a new electronic circuit placement layout;
- and
- identify HTF DRC violations based on the fix rates of the DRC violations of the new electronic circuit placement layout;
- and
- an engineering change order (ECO) tool configured to fix the HTF DRC violations.
9 more elements
A method, comprising:
- training a machine learning model with a plurality of electronic circuit placement layouts, the machine learning model being configured to predict hard-to-fix (HTF) design rule check (DRC) violations, information of the plurality of electronic circuit placement layouts being stored in a database;
- extracting a feature combination of a new electronic circuit placement layout;
- calculating fix rates of DRC violations present on the new electronic circuit placement layout;
- identifying the HTF DRC violations among the DRC violations based on the fix rates of the DRC violations of the new electronic circuit placement layout,
- wherein identifying the HTF DRC violations based on the fix rates of the DRC violations of the new electronic circuit placement layout comprises:
- comparing the fix rates of the DRC violations of the new electronic circuit placement layout to a threshold fix rate;
- and
- determining that the fix rates of the DRC violations of the new electronic circuit placement layout are HTF DRC violations, when the fix rates of the DRC violations of the new electronic circuit placement layout are below the threshold fix rate;
- comparing the feature combination with existing feature combinations corresponding to the plurality of electronic circuit placement layouts;
- and
- adding information of the new electronic circuit placement layout to the database when the feature combination is new.
8 more elements
A method, comprising:
- training a machine learning model with a plurality of electronic circuit placement layouts, the machine learning model being configured to predict hard-to-fix (HTF) design rule check (DRC) violations, information of the plurality of electronic circuit placement layouts being stored in a database,
- wherein training the machine learning model comprises:
- extracting a plurality of feature combinations of the plurality of electronic circuit placement layouts;
- calculating fix rates of DRC violations present on the plurality of electronic circuit placement layouts;
- and
- establishing a relationship between the fix rates and the plurality of feature combinations;
- extracting a feature combination of a new electronic circuit placement layout;
- predicting, by the machine learning model, fix rates of DRC violations present on the new electronic circuit placement layout by:
- predicting the fix rates of the DRC violations based on the feature combination of the new electronic circuit placement layout and the established relationship between the fix rates and the plurality of feature combinations;
- and
- normalizing the feature combination of the new electronic circuit placement layout;
- comparing the feature combination with existing feature combinations corresponding to the plurality of electronic circuit placement layouts;
- and
- adding information of the new electronic circuit placement layout to the database when the feature combination is new.
11 more elements
Dependencies are inferred from the claim text.