Semiconductor process technology assessment

A method of generating a new technology file for process technology assessment, comprising:

• defining a scope of the process technology assessment by assessing changes between an original process technology that includes original layout parameters and a new process technology that includes first layout parameters;
• modeling a first object in an integrated circuit into a first resistance in the first process technology and a first capacitance in the first process technology;
• modeling a second object in the integrated circuit into a second resistance in the first process technology and a second capacitance in the first process technology;
• generating a first resistance scaling factor that is based on the first resistance and the original process technology and a first capacitance scaling factor that is based on the first capacitance and the original process technology;
• generating a second resistance scaling factor that is based on the second resistance and the original process technology and a second capacitance scaling factor that is based on the second capacitance and the original process technology;
• and
• integrating the first resistance scaling factor, the first capacitance scaling factor, the second resistance scaling factor, the second capacitance scaling factor, and an original technology file corresponding to the original process technology to generate the new technology file, wherein the new technology file is utilized by an electronic design automation (EDA) tool for simulation of the integrated circuit.

A system, comprising:

• a processor;
• and
• a memory accessible by the processor, the memory storing instructions that when executed by the processor execute a method comprising:
• defining a scope of the process technology assessment by assessing changes between an original process technology that includes original layout parameters and a first process technology that includes first layout parameters;
• modeling a first object in an integrated circuit into a first resistance in the first process technology and a first capacitance in the first process technology;
• modeling a second object in the integrated circuit into a second resistance in the first process technology and a second capacitance in the first process technology;
• generating a first resistance scaling factor that is based on the first resistance and the original process technology and a first capacitance scaling factor that is based on the first capacitance and the original process technology;
• generating a second resistance scaling factor that is based on the second resistance and the original process technology and a second capacitance scaling factor that is based on the second capacitance and the original process technology;
• inputting the first resistance scaling factor, the first capacitance scaling factor, the second resistance scaling factor, and the second capacitance scaling factor into an electronic design automation (EDA) tool;
• inputting an original technology file corresponding to the original process technology into the EDA tool;
• and
• utilizing, by the EDA tool, the first resistance scaling factor, the first capacitance scaling factor, the second resistance scaling factor, the second capacitance scaling factor, and the original technology file for simulation of the integrated circuit.