Dataflow Based Analysis Guidance to Mapper for Buffers Allocation in Multicore Architectures
AssigneeXilinx, Inc.
InventorAjit K. Agarwal
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Abstract
Providing dataflow based guidance for buffer allocation in a multicore circuit architecture includes converting, using computer hardware, an application specified in a high-level programming language into an intermediate representation. Buffers of dataflows of the intermediate representation are detected. Determining whether the buffers are independent or dependent based on an analysis of the dataflows of the intermediate representation. Buffer constraints are generated. The buffer constraints specify whether the buffers are independent and dictate a mapping of the buffers in the multicore circuit architecture.
Claims20
A method, comprising:
- converting, using computer hardware, a design specified in a high-level programming language into an intermediate representation, wherein the design is for a multicore circuit architecture;
- detecting buffers of dataflows of the intermediate representation;
- determining whether the buffers are independent or dependent based on an analysis of the dataflows of the intermediate representation performed using the computer hardware;
- and
- generating buffer constraints, wherein the buffer constraints specify whether the buffers of the intermediate representation are independent and provide guidance for mapping the buffers in the multicore circuit architecture.
A system, comprising:
- one or more hardware processors configured to initiate operations including:
- converting a design specified in a high-level programming language into an intermediate representation, wherein the design is for a multicore circuit architecture;
- detecting buffers of dataflows of the intermediate representation;
- determining whether the buffers are independent or dependent based on an analysis of the dataflows of the intermediate representation;
- and
- generating buffer constraints, wherein the buffer constraints specify whether the buffers of the intermediate representation are independent and provide guidance for mapping the buffers in the multicore circuit architecture.
A computer program product comprising one or more computer readable storage mediums having program instructions embodied therewith, the program instructions executable by computer hardware to cause the computer hardware to initiate executable operations comprising:
- converting a design specified in a high-level programming language into an intermediate representation, wherein the design is for a multicore circuit architecture;
- detecting buffers of dataflows of the intermediate representation;
- determining whether the buffers are independent or dependent based on an analysis of the dataflows of the intermediate representation;
- and
- generating buffer constraints, wherein the buffer constraints specify whether the buffers of the intermediate representation are independent and provide guidance for mapping the buffers in the multicore circuit architecture.
Dependencies are inferred from the claim text.