Implementing burst transfers for predicated memory accesses in loop bodies for high-level synthesis

A system, comprising:

• one or more hardware processors configured to initiate operations including:
• generating an intermediate representation of a design specified in a high-level programming language, wherein the design is for an integrated circuit;
• determining loop predicate information for one or more conditional statements within a loop body of the intermediate representation;
• determining that a plurality of memory accesses of the loop body guarded by the one or more conditional statements are sequential memory accesses that execute in different iterations of the loop body based on the predicate information;
• and
• modifying the intermediate representation by inserting one or more intrinsics therein indicating that the sequential memory accesses are to be implemented using a burst transfer mode of the integrated circuit.

A computer program product comprising one or more computer readable storage mediums having program instructions embodied therewith, the program instructions executable by computer hardware to cause the computer hardware to initiate executable operations comprising:

• generating an intermediate representation of a design specified in a high-level programming language, wherein the design is for an integrated circuit;
• determining loop predicate information for one or more conditional statements within a loop body of the intermediate representation;
• determining that a plurality of memory accesses of the loop body guarded by the one or more conditional statements are sequential memory accesses that execute in different iterations of the loop body based on the predicate information;
• and
• modifying the intermediate representation by inserting one or more intrinsics therein indicating that the sequential memory accesses are to be implemented using a burst transfer mode of the integrated circuit.