Signal processor and signal processing system

A signal processor, comprising:

• a first terminal, into which one of a clock signal and a data signal is input;
• a second terminal, into which another one of the clock signal and the data signal is input;
• a storage unit, in which an address map is set to define an address permitting data writing and an address prohibiting data writing;
• a designation unit, configured to designate the address map set in the storage unit;
• and
• a processing unit, configured to write a data based on the data signal to the storage unit according to the address map designated by the designation unit, wherein the designation unit
• designates a first address map when the clock signal is input into the first terminal and the data signal is input into the second terminal, and
• designates a second address map different from the first address map when the data signal is input into the first terminal and the clock signal is input into the second terminal.