Multiple-core memory controller
AssigneeQUALCOMM Incorporated
InventorsPankaj Deshmukh, Shyamkumar Thoziyoor, Vishakh Balakuntalam Visweswara, Jungwon Suh, Subbarao Palacharla
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Abstract
This disclosure provides systems, methods, and devices for memory systems that support operating a least portions of a memory core at a frequency lower than a memory clock to reduce power consumption and cost. In a first aspect, a memory controller includes a first core for scheduling a first memory operation for a first portion of a clock cycle of the memory clock and includes a second core for scheduling a second memory operation for a second portion of the clock cycle of the memory clock. Other aspects and features are also claimed and described.
Claims30
An apparatus, comprising:
- a memory controller operating based on a first clock at a memory controller clock frequency, wherein the memory controller is:
- comprised of a memory physical (PHY) interface operated based on a memory clock at a memory clock frequency and of a plurality of cores, each of the plurality of cores operated at the memory controller clock frequency which is less than the memory clock frequency,
- coupled to a memory through a channel by the memory physical (PHY) interface,
- configured to access data stored in the memory through the channel and the memory physical (PHY) interface, and
- configured to perform operations comprising:
- scheduling, by a first core of the plurality of cores, a first memory operation for a first portion of a clock cycle of the memory clock;
- scheduling, by a second core of the plurality of cores, a second memory operation for a second portion of the clock cycle of the memory clock;
- and
- transmitting, by the memory physical (PHY) interface during the clock cycle of the memory clock, first signals corresponding to the first memory operation and second signals corresponding to the second memory operation.
A method, comprising:
- scheduling a first memory operation for a first portion of a clock cycle of a memory clock in a first core of a memory controller;
- scheduling a second memory operation for a second portion of a clock cycle of the memory clock in a second core of the memory controller;
- and
- transmitting, to the memory, first signals corresponding to the first memory operation during the first portion of the clock cycle and second signals corresponding to the second memory operation during the second portion of the clock cycle, wherein the memory clock has a memory clock frequency higher than a memory controller frequency of the memory controller.
An apparatus, comprising:
- a memory;
- a host device configured to communicate with the memory through a channel,
- the host device comprising a memory controller coupled to the channel, wherein the memory controller is:
- comprised of a memory physical (PHY) interface operated based on a memory clock at a memory clock frequency and of a plurality of cores, each of the plurality of cores operated at a memory controller clock frequency less than the memory clock frequency,
- coupled to a memory through a channel by the memory physical (PHY) interface,
- configured to access data stored in the memory through the channel and the memory physical (PHY) interface, and
- configured to perform operations comprising:
- scheduling, by a first core of the plurality of cores, a first memory operation for a first portion of a clock cycle of the memory clock;
- scheduling, by a second core of the plurality of cores, a second memory operation for a second portion of the clock cycle of the memory clock;
- and
- transmitting, by the memory physical (PHY) interface during the clock cycle of the memory clock, first signals corresponding to the first memory operation and second signals corresponding to the second memory operation.
Dependencies are inferred from the claim text.