System recovery during cgi-wl defect

A storage device, comprising:

• a plurality of blocks of non-volatile memory, each block including a plurality of word lines;
• a plurality of interconnects between multiple ones of the blocks, the plurality of interconnects being within an interconnect set;
• and
• a controller configured to:
• determine a logical address pattern associated with the multiple ones of the blocks, the multiple ones of the blocks respectively including a program failure,
• determine whether the logical address pattern is associated with the interconnect set for the multiple ones of the blocks,
• determine, in response to the logical address pattern being associated with the interconnect set, a word line from the plurality of word lines that is associated with the program failures, the word line being a common word line associated with the program failures in the multiple ones of the blocks, and
• refrain from programming the common word line during respective program operations in the multiple ones of the blocks.

A storage device, comprising:

• a plurality of blocks of non-volatile memory, each block including a plurality of word lines;
• a plurality of interconnects between multiple ones of the blocks, the plurality of interconnects being within an interconnect set;
• a first register including a first set of bits corresponding to the plurality of interconnects;
• a second register including a second set of bits corresponding to the plurality of word lines;
• and
• a controller configured to:
• determine the interconnect set associated with program failures in the multiple ones of the blocks,
• determine, in response to the determination of the interconnect set, a word line from the plurality of word lines that is associated with the program failures, the word line being a common word line to the multiple ones of the blocks, and
• provide a command to program the plurality of word lines respectively in at least one of the multiple ones of the blocks, the common word line being excluded from programming in response to a value of the first register and a value of the second register.