Enhanced read performance for memory data word decoding using power allocation based on error pattern detection
AssigneeMicron Technology, Inc.
InventorsNitul Gohain, Jameer Mulani, Jonathan S. Parry
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AssigneeMicron Technology, Inc.
InventorsNitul Gohain, Jameer Mulani, Jonathan S. Parry
Estimating the term…
Methods, systems, and devices to enhance read performance for memory data word decoding using power allocation based on error pattern detection in both QLC and TLC in both QLC and TLC products are described. A plurality of data words may be processed using a first decoder engine of a decoder of a memory device according to a first power setting. The decoder may detect a pattern of errors in the plurality of data words. The decoder may further communicate a status signal based on detecting the pattern of errors. The resource manager may allocate based on the status signal, a second amount of power credits to the decoder. The decoder may process a portion of the plurality of data words using a second decoder engine according to the second amount of power credits.
A memory device, comprising:
A method, comprising:
An apparatus, comprising:
Dependencies are inferred from the claim text.