Techniques For Transposing A Matrix Using A Memory Block
AssigneeIntel Corporation
InventorHong Shan Neoh
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Abstract
A circuit system includes a memory block and first and second processing circuits. The first and second processing circuits store a matrix in the memory block by concurrently writing first and second rows or columns of the matrix to first and second regions of storage in the memory block, respectively. The first and second processing circuits transpose the matrix to generate a transposed matrix by concurrently reading first and second rows or columns of the transposed matrix from third and fourth regions of storage in the memory block, respectively.
Claims20
An integrated circuit comprising:
- a memory block;
- a first processing circuit comprising a first transpose engine that writes a first column or row of a matrix to a first region of storage in the memory block, wherein the first transpose engine is in series with a parallel math engine;
- and
- a second processing circuit comprising a second transpose engine that writes a second column or row of the matrix to a second region of storage in the memory block, wherein the first and the second transpose engines write the first and the second columns or rows of the matrix to the first and the second regions of storage in parallel, and
- wherein the first and the second transpose engines transpose the matrix to generate a transposed matrix by reading first and second columns or rows of the transposed matrix from third and fourth regions of storage, respectively, in the memory block in parallel.
A method for transposing a matrix to generate a transposed matrix, the method comprising:
- writing a first column or row of the matrix to a first region of storage in a memory block using a first transpose engine operating on a first processing circuit, wherein the first transpose engine is in series with a parallel math engine;
- writing a second column or row of the matrix to a second region of storage in the memory block using a second transpose engine operating on a second processing circuit in parallel with the first transpose engine writing the first column or row of the matrix to the first region of storage;
- reading a first column or row of the transposed matrix from a third region of storage in the memory block using the first transpose engine operating on the first processing circuit;
- and
- reading a second column or row of the transposed matrix from a fourth region of storage in the memory block using the second transpose engine operating on the second processing circuit in parallel with the first transpose engine reading the first column or row of the transposed matrix from the third region of storage.
A circuit system comprising:
- a memory block;
- and
- first and second processing circuits, wherein first and second transpose engines operating on the first and the second processing circuits store a matrix in the memory block by the first transpose engine writing a first row or column of the matrix to a first region of storage in the memory block concurrently with the second transpose engine writing a second row or column of the matrix to a second region of storage in the memory block, wherein the first transpose engine is in series with a parallel math engine, and
- wherein the first and the second transpose engines transpose the matrix to generate a transposed matrix by the first transpose engine reading a first row or column of the transposed matrix from a third region of storage in the memory block concurrently with the second transpose engine reading a second row or column of the transposed matrix from a fourth region of storage in the memory block.
Dependencies are inferred from the claim text.