Multi-bit analog multiplication and accumulation circuit system

A multi-bit analog multiplication and accumulation circuit system for performing a multiplication and accumulation operation on a plurality of four-bit input data and four-bit weight data during one CIM period, including:

• a plurality of analog multiplication circuits for respectively performing multiplications on four-bit input data and four-bit weight data, respectively, wherein each analog multiplication circuit includes four capacitor switch arrays, each performing multiplications on one bit of the four-bit input data and the four-bit weight data;
• a first accumulation line, a second accumulation line, a third accumulation line and a fourth accumulation line, wherein each accumulation line outputs an accumulation of multiplications performed by each capacitor switch array of each analog multiplication circuit on one bit of the four-bit input data and the four-bit weight data;
• and
• a binary place value combiner electrically connected to the first accumulation line, the second accumulation line, the third accumulation line and the fourth accumulation line for summing up accumulated results outputted by each accumulation line with corresponding binary place value, so as to output a final multiplication and accumulation result of the CIM period.