In-memory computation system with compact storage of signed computational weight data

An in-memory computation circuit, comprising:

• a memory array including a plurality of memory cells arranged in a matrix with plural rows and plural columns, wherein groups of memory cells store computational weights for an in-memory compute (IMC) operation that is performed with a first multiply and accumulate (MAC) elaboration and a second MAC elaboration, each row of groups of memory cells including a positive word line coupled to a first memory cell in each group of memory cells and a negative word line coupled to a second memory cell in each group of memory cells, and each column of groups of memory cells including a bit line coupled to the first and second memory cells of each group of memory cells;
• a row controller circuit configured to receive signed coefficient data for the IMC operation and:
• a) generate during the first MAC elaboration a pulsed word line signal for application to the positive word line when the signed coefficient data is positive, and generate a pulsed word line signal for application to the negative word line when the signed coefficient data is negative;
• and b) generate during the second MAC elaboration a pulsed word line signal for application to the negative word line when the signed coefficient data is positive, and generate a pulsed word line signal for application to the positive word line when the signed coefficient data is negative;
• and
• a column processing circuit coupled to the bit line and configured to:
• a) sense a first analog signal developed on the bit line during the first MAC elaboration;
• and b) sense a second signal developed on the bit line during the second MAC elaboration.