Novel data cache scheme for high performance flash memories

A computer-implemented method, comprising:

• receiving, by a memory controller from a host, a write command comprising data to be written into a flash memory;
• splitting, by the memory controller, the data into a first portion and a second portion;
• storing, by the memory controller, the first portion into a static random-access memory (SRAM) in the memory controller;
• storing, by the memory controller, the second portion into a dynamic random-access memory (DRAM) communicatively coupled with the memory controller;
• initiating, by a flash translation layer in the memory controller, a configuration operation corresponding to the write command;
• fetching, by the memory controller, the first portion from the SRAM and the second portion from the DRAM in response to the flash translation layer indicating a ready status to store the data into the flash memory;
• combining, by the memory controller, the fetched first portion and the fetched second portion;
• and
• storing, by the flash translation layer, the combined first portion and the second portion into the flash memory.

Non-transitory computer-readable storage media storing instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:

• receiving, by a memory controller from a host, a write command comprising data to be written into a flash memory;
• splitting, by the memory controller, the data into a first portion and a second portion;
• storing, by the memory controller, the first portion into a static random-access memory (SRAM) in the memory controller;
• storing, by the memory controller, the second portion into a dynamic random-access memory (DRAM) communicatively coupled with the memory controller;
• initiating, by a flash translation layer in the memory controller, a configuration operation corresponding to the write command;
• fetching, by the memory controller, the first portion from the SRAM and the second portion from the DRAM in response to the flash translation layer indicating a ready status to store the data into the flash memory;
• combining, by the memory controller, the fetched first portion and the fetched second portion;
• and
• storing, by the flash translation layer, the combined first portion and the second portion into the flash memory.