Techniques for coupled host and memory dies

A method, comprising:

• receiving, at a first interface block of a first semiconductor die, first memory access command signaling from a host processor of the first semiconductor die;
• transmitting, by the first interface block, second memory access command signaling based at least in part on receiving the first memory access command signaling from the host processor;
• receiving, at a second interface block of a second semiconductor die coupled with the first semiconductor die, the second memory access command signaling transmitted by the first interface block;
• and
• accessing, using the second interface block, a set of one or more memory arrays of the second semiconductor die based at least in part on receiving the second memory access command signaling.

An apparatus comprising circuitry configured to:

• receive, at a first interface block of a first semiconductor die, first memory access command signaling from a host processor of the first semiconductor die;
• transmit, by the first interface block, second memory access command signaling based at least in part on receiving the first memory access command signaling from the host processor;
• receive, at a second interface block of a second semiconductor die coupled with the first semiconductor die, the second memory access command signaling transmitted by the first interface block;
• and
• access, using the second interface block, a set of one or more memory arrays of the second semiconductor die based at least in part on receiving the second memory access command signaling.