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US 2024/0176495 A1Published application
Memory device and operating method for controlling data output time
AssigneeSK hynix Inc.
InventorDong Hun KWAK
Life of this patent
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Abstract
According to the present disclosure, a memory device includes a memory cell, a delay information storage configured to store delay information associated with a time at which data stored in the memory cell is output, and an operation controller configured to output the data to an external device after delaying a time corresponding to the delay information from a time of discharging a voltage provided to the memory cell.
Claims20
A memory device, comprising:
- a memory cell;
- a delay information storage configured to store delay information associated with a time at which data stored in the memory cell is output;
- and
- an operation controller configured to output the data to an external device after delaying a time corresponding to the delay information from a time of discharging a voltage provided to the memory cell.
1 more element
A memory device, comprising:
- a state signal output circuit configured to output a state signal indicating a state being capable of receiving a command from an external device;
- a delay information storage configured to store delay information regarding a delay time for outputting of the state signal;
- and
- an operation controller configured to control the state signal output circuit to output the state signal after the delay time passes, the delay time starting from a time at which a voltage used in an internal operation starts to be discharged after the internal operation has been performed.
1 more element
A memory device, comprising:
- a delay information generator configured to generate output delay information used to delay an outputting of data by using an input from an external device;
- a state signal output circuit configured to output a state signal to the external device, the state signal indicating a state being capable of receiving a command from the external device;
- and
- an operation controller configured to control the state signal output circuit to output the state signal after a time, corresponding to the output delay information, passes when an internal operation has been completed.
1 more element
Dependencies are inferred from the claim text.