Storage device for reducing delay of parity operation, controller and method for operating controller

A controller comprising:

• a buffer memory;
• a first processor configured to, in a parity operation mode in which a parity value for data to be written to a memory located outside is generated, manage state information of at least one of a plurality of buffer areas included in the buffer memory, and to output a control signal according to the state information;
• and
• a second processor configured to operate according to the control signal of the first processor, and to write the parity value to the buffer memory.

A method for operating a controller, comprising:

• allocating at least one among a plurality of buffer areas included in a buffer memory, as a parity area;
• generating a parity value for data to be written to a predesignated memory area of a memory located outside, and writing the parity value to the parity area;
• writing, when writing of the parity value for the data to be written to the predesignated memory area is completed, the parity value to the memory located outside;
• and
• initializing the parity area to which the parity value is written.